Pulse rise time and amplitude detector



Nov. 24, 1970 M. D. SLAYDEN ET 3,543,159

PULSE RISE TIME AND AMPLITUDE DETECTOR Filed Nov.- 16, 1967 2Sheets-Sheet 1 GATE 5 E AT ISL s NER OR v u 27 P 35 E, A INPUT AND 3STORED 5 g BUFFER GATE D OUTPUT DELAY GENERATOR C FIG. I

MURREL D. SLAYDEN, FIG. 2 HUGH w. STALEY,

wTORfi) BY 44. s aw,

ATTORNEYS NOV. 24, 1970 SLAYDEN ET AL 3,543,159

PULSE RISE TIME AND AMPLITUDE DETECTOR Filed Nov. '16. 1967 zSheets-Sheet z I A v TIME MURREL D. SLAYDEN, HUGH W STALEY,

INVENTOR.(S)

A TTORNEYS Int. Cl. G04f 9/00 US. Cl. 324-181 PULSE RISE TIME Murrel D.Slayden,

3 Claims ABSTRACT OF THE DISCLOSURE An apparatus for detecting pulseswhich exceed a specified rise time from a first to a second amplitudeincluding an input buffer for receiving the pulse and for simultaneouslyapplying it to a gate generator and to a delay generator. The gategenerator output is coupled to an AND gate and functions to open the ANDgate for a time period equal to the specified rise time after theincoming pulse has reached the first amplitude. The delay generatoroutput is also connected to the AND gate and functions to produce apulse at the time that the incoming pulse exceeds the second amplitude.If the AND gate is still being held open by the presence of the gategenerator pulse when the delay generator pulse arrives, this pulse willpass through the AND gate and will be indicative of a no-go condition.

BACKGROUND OF THE INVENTION The invention described herein was made byemployees of the United States Government and may be manufactured andused by or for the Government for governmental purposes without thepayment of any royalties thereon or therefor.

This invention relates generally to an electrical testing apparatus andmore particularly to a system of evaluating the rise time and amplitudeof an electrical pulse to determine whether the pulse exceeds thepredetermined toleran-ce limits.

As the development of space vehicleshas progressed in size andcomplexity, the complexity of verifying the flight readiness of eachvehicle has increased. Of particular concern has been the detection ofundesirable transients that exceed a certain voltage level and rise timeso as to cause a malfunction of a device having a voltage-rise timeresponse characteristic. As an example, a typical computer input pulsecould have a specified rise time of between 20 to 180 nanoseconds. Thus,in this case any transient pulse having a rise time between these limitsand sufficient amplitude could energize the monitored circuitry, therebycausing a malfunction.

The increase in complexity of detecting such transients has resulted inpart from the greater probability that electrical systems on the vehiclewill interfere with one another by the conduction of undesirabletransients through common'power lines, ground return cables, data linesor the like. A second reason for the increase in complexity arisesbecause of the great number of points which must be monitoredsimultaneously during a complete test, since even after a criticalselection of monitor points (such as points in which a transient couldcause a malfunction in the system that is necessary for the flight tocontinue as planned) it is often necessary to monitor several hundredpoints.

In the past, the monitoring of these points was accomplished byapparatus designed to detect only the amplitude of the transients anddid not allowfor the testing of the dynamic characteristics of thetransient. As a digital circuit is responsive not only to the amplitudeof the pulse applied to it bua also to the rise time of the UnitedStates Patent 'ice applied pulse little confidence could be given to thetest results.

SUMMARY OF THE INVENTION According to the present invention, it has beenfound that a detector can be made for determining whether a transientexceeds a specified rise time from first to second predeterminedamplitudes by applying the transient to an input buffer whichsimultaneously applies the transient to a first and a second amplitudedetector. The first amplitude detector functions to produce a pulsehaving a width equal to the specified rise time when the transientexceeds the first predetermined amplitude and the second amplitudedetector functions to produce a pulse when the incoming transientexceeds the second predetermined amplitude. The outputs from the firstand the second amplitude detectors are applied to an AND gate so that ifan output pulse appears simultaneously from the first and secondamplitude detectors a no-go condition will be indicated.

Accordingly, one object of this invention is to provide a sensor fordetecting transients which exceed a specified rise time and amplitude.

Another object of this invention is to provide a sensor for monitoringelectrical devices having a voltage rise time response characteristic.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantagesof this invention will be more apparent upon reference to the followingspecifications, appended claims and drawings wherein:

FIG. 1 is a block diagram of the detector constructed in accordance withthis invention wherein the blocks of the diagram represent the variouselements of the system and the solid lines illustrate the manner inwhich the elements are electrically interconnected with one another todetect transients which exceed a specified amplitude and rise time.

FIG. 2 is a schematic illustration of the system of FIG. 1.

FIG. 3 illustrates waveforms found in the system of FIGS 1 and 2 for onespecific set of tolerance limits.

As shown in the block diagram representation of FIG. 1, the pulseamplitude and rise time sensor comprises an input buffer 11 having aninput terminal 13 and output leads 15 and 19. The input terminal isadapted to be connected to the circuit being monitored, the first inputbuifer output lead 15 is coupled to a gate generator 17 and the secondinput buffer output lead 19 is coupled to a delay generator 21. The gategenerator output lead 23 and the delay generator output lead 25 arecoupled to AND gate 27, the latter having its output lead 29 connectedto a stored output 31. The output lead 33 of the stored output 31 iscoupled to output terminal 35.

The operation of the pulse rise time and amplitude detector of FIG. 1 isbest described with refernce to the representive waveforms shown in FIG.3. FIG. 3a shows an exemplary negative going transient pulse A reachinga first refernce voltage level v at time t and a second referencevoltage level v;, at time t The first and second reference voltagelevels may conveniently be the 10% and the amplitude of a known negativedigital pulse. In operation, the transient pulse A is coupled to theinput terminal 13 and energizes input buffer 11. The input butter 11 isutilized to provide a high input impedance for the sensor relative tothe circuit being monitored and couples the incoming pulse A to the gategenerator 17 and the the delay generator 21.

The gate generator 17 comprises an amplitude detector which whentriggered has a pulse output of adjustable width and very low rise andfall times. The threshold level of the gate generator 17 is set so thatthe gate generator will be triggered when the incoming transient pulse Aexceeds the first reference level v of the known digital pulse and thewidth of the pulse output is adjusted to the specified rise time for thecircuit being monitored. The output pulse of the gate generator 17 isillustrated by the Waveform of FIG. 3b, where a positive-going pulse Bis initiated at time 2 and continues to time t Thus, the time interval tto t represents the maximum specified rise time from the first referencelevel v to the second reference level v for the digital circuity beingmonitored. The gate generator 17 output pulse B is thereafter applied tolead 23 to open the AND gate 27 for the time period t to t The delaygenerator 21 also comprises an amplitude detector, which when triggeredhas a pulse output having very low rise and fall times, however itsthreshold level is set so that the delay generator will be triggeredwhen the incoming transient pulse A exceeds the second reference level vof the known digital pulse of the circuit being monitored. The outputpulse of the delay generator 21 is illustrated in FIG. 3c, where apositive going pulse C is initiated at time 1 and continues to time 1The delay generator 21 output pulse C is thereafter applied to the inputlead 25 of the AND gate 27. As shown in FIGS. 3b and 3c, the two signalsapplied to the AND gate 27 are positive during that time interval t to tand the AND gate will be activated and will transfer the pulse on lead25 to lead 29. This signal is shown in FIG. 3d as a positive going pulseD for the interval between time t and time t A memory circuit such asstored output 31 may be provided so that the detector circuit may beread at a convenient time.

-In the example shown, the incoming pulse A shown in FIG. 3a reached thesecond reference voltage level v,, at time 1 at which time the AND gate27 was still held open by the output pulse B from the gate generator 17.It will be seen however that if the incoming pulse A reaches the secondreference voltage level v after time t the AND gate will no longer beheld open by the pulse output B of the gate generator 17 and no pulsewill pass through AND gate 27. Also should the incoming pulse A remainbelow the second voltage level v no pulse will pass through the AND gate27 as the threshold level of the delay generator will not be exceeded.From the foregoing it will be seen that the width of the output pulse ofthe gate generator 17 determines the critical rise time of the pulsebeing monitored and the threshold level of the delay generator 21determines the critical amplitude of the pulse being monitored.

FIG. 2 is a schematic circuit diagram of the pulse rise time andamplitude sensor of FIG. 1. The input buffer 11 for instance, consistsof PNP transistor 41 having its base connected to input terminal 13 andits emitter connected to a source of positive potential 43 via theserial connection of resistors 45 and 49, the midpoint of which iscoupled to ground via capacitor 49. The collector of transistor 41 isconnected to a source of negative potential 51 via resistor 53. Thecollector of transistor 41 is also coupled to input buffer output lead15 via the serial connection of resistor 55 and capacitor 57 and to theinput buffer output lead 19 via the serial connectionof resistor 59 andcapacitor 61. Capacitors 57 and 61 provide for AC coupling between thecollector of transistor 41 and the respective bases of NPN transistors63 and 65, the latter forming the input to the gate generator 17 and tothe delay generator 21 respectively.

The gate generator 17 comprises a one-shot multivibrator in which theemitter of transistor 63 is coupled to ground and the collector oftransistor 63 is coupled to a positive voltage source 67 via resistor69. The collector of transistor 63 is also coupled to one terminal ofvariable capacitor 71, the other terminal of capacitor 71 beingconnected to the base of NPN transistor 73, and to the midpoint of theserial connection of variable resistors 75 and 77, which resistorsextend between the positive voltage source 67 and ground. The base oftransistor 63- across. The collector of transistor 73 is coupled to thesource of positive potential 67 by resistor 89 and to the AND gate inputlead 23. The emitter of transistor 73 is connected to ground.

It will be seen that with the circuity disclosed, the gate generator 17is arranged so that during the quiescent state transistor 63 isnon-conducting and transistor 73 is conducting. The positive potentialsource 67 provides the collector bias voltage for transistor 63 and 73and forward bias for transistor 73 by the voltage divider networkconsisting of resistors 75 and 77. A reverse bias is provided tomaintain transistor 63 cut-off by the serial connection of resistors 89,and 81 and variable resistor 83 between the negative potential source 79and the positive potential source 67. It will thus be seen that in thequiescent state the collector of transistor 73 is essentially at groundpotential.

However, when a negative going pulse is applied to input terminal 13, anamplified and inverted pulse is applied to lead 15 and the base oftransistor 63 by means of transistor 41, resistor 55 and capacitor 57.When the positive going pulse on the input buffer output lead 15 and thebase of transistor 63 reaches the threshold level of the gate generator17, (determined by the setting of. resistor 83) the base of transistor63 is driven positive causing transistor 63 to be turned on and causingtransistor 73 to turn off in the well known manner. With transistor 73cut-off, the potential of its collector rises essentially to the valueof the positive voltage source 67 and provides a positive going pulseonthe AND gate input lead 23, the length of which is determined by thetime constant of variable resistors 77 and 75 and variable capacitor 71.

In operation, the resistance of variable resistor 83 is adjusted so thatthe gate generator 17 will be triggered when the incoming transientpulse A exceeds the first voltage reference level v and the timeconstant of resistors 77 and 75 and capacitor 71 is adjusted so that thewidth of the output pulse of the gate generator 17 equals the specifiedrise time between the first voltage reference v and the second voltagereference level v The delay generator 21 also comprises a one-shotmultivibrator and is of similar construction to the. gate generator 17.As shown in FIG. 2, the output lead 19 of the input buffer 11 is coupledto the base of-tr-ansistor 65. The collector of transistor 65 is coupledto the positive voltage source 6 7 by resistor 91 and lead 93 and iscoupled to the base of transistor 95 via variable capacitor 97. Theemitter of transistor 65 is coupled to ground as shown and the base oftransistor 65 is coupled to the collector of transistor 95 via resistor99 having capacitor 101 connected thereacross and is additionallyconnected to a negative potential source 103 by the serial connection ofresistor 105 and variable resistor 107. The collector of transistor 95is connected to input lead 25 of the AND gate 27 and to the source ofpositive potential 67 via resistor 109 and lead 93. The emitter oftransistor 95 is connected to ground and the base is connected to themidpoint of variable resistors 111 and 113 which extend between thepositive potential source 67 and ground.

The operation of the delay generator 21is similar to that of the gategenerator 17 as transistor 65 is quiescently held in the non-conductingstate and transistor 95 is in the conducting state. The operation of thedelay generator 21 differs however from the gate generator 17 in thatvariable resistor 107 is adjusted so that transistor 65 remains in itsnon-conductive state until the amplitude of the tramsient pulse appliedto terminal 13 has reached the second voltage reference level v It willthus be seen that in the absence of a pulse greater in value than thesecond voltage reference level being impressed on input terminal 13 andwith transistor 95 normally conducting the collector of transistor 95will be essentially at ground potential. However, when the input to thedelay generator 21 exceeds the threshold level of the delay generator,the base of transistor 65 will be driven positive with respect to theemitter and transistor 65 will conduct thereby causing transistor 95 toturn oif in the well known manner. With transistor 95 cut-off, thepotential of its collector rises essentially to the value of thepositive voltage source 67 and provide a positive going pulse on the ANDgate input lead 25 as shown in FIG. 30.

In order to determine whether there is time coincidence between thepulsed output of the gate generator 17 and the delay generator 21, ANDgate 27 is provided consisting of diodes 115 and 117. Diode 115 isconnected to the collector of transistor 95 and also to output terminal119 which is also connected to the positive potential source 67 byresistor 121. Diode 117 is connected to the collector of transistor 73and also to the output lead 29. In the well known manner output terminal119 will remain essentially at ground potential when either transistor73 or transistor 95 is conducting but will approach the positivepotential level source 67 when transistors 95 and 73 are simultaneouslynon-conductive.

It is of course to be recognized that the exemplary transient pulseshown in FIG. 3a exceeded the amplitude of the second voltage referencelevel v in the time interval t to t and thus a pulse as shown in FIG. 3dappeared on the output of the AND gate 31. However, if transient pulseapplied to input terminal 13 never exceeded the second voltage referencelevel v the threshold level of the delay generator would never beexceeded and no pulse would be produced by the delay generator 21 andthe pulse appearing on the gate generator output lead 23 cannot passthrough the AND gate 27. Additionally, if the transient pulse shouldexceed the second reference level v after the time interval t, to t thepulse from the gate generator 17 will have ended and again no pulse willpass through the AND gate 27.

It will now be seen that the present invention provide very fastoperation with digital accuracy and the invention can be employed toevaluate pulses of any amplitude and rise time by adjustment of thethreshold level of the delay generator 21 and the width of the pulse ofthe gate generator 17. It will further be seen that a go no-go typeoutput is obtained that may easily be stored if desired and read-out atany time.

We claim:

1. An apparatus for detecting a pulse exceeding a predeterminedamplitude and rise time from a first amplitude to the predeterminedamplitude comprising:

an input circuit for receiving an input pulse to be evaluated;

gate generator means coupled to said input circuit for producing asubstantially rectangularly shaped gating pulse in response to the inputpulse exceeding a first amplitude, said gating pulse having a widthequal to a predetermined rise time between said first amplitude and saidpredetermined amplitude;

delay generator means coupled to said input circuit for producing adelay pulse in response to the input pulse exceeding said predeterminedamplitude;

a coincidence circuit connected to receive said gating pulse and saiddelay pulse for producing an output pulse when any portions of thegating pulse and the delay pulse are in time coincidence.

2. A pulse amplitude and rise time detector as claimed in claim 1wherein:

(a) said input circuit includes means for generating a signalproportional to the input pulse;

(b) said gate generator includes amplitude detecting means forinitiating said gating pulse when said generated signal exceeds a firstthreshold level and;

(c) said delay generator includes amplitude detecting means forinitiating said delay pulse when said generated signal exceeds a secondthreshold level.

3. A pulse amplitude and rise time detector as claimed in claim 1wherein:

(a) said gate generator comprises a first one-shot multivibrator;

(b) said delay'generator comprises a second one-shot multivibrator.

References Cited UNITED STATES PATENTS 3,204,180 8/1965 Bray et a1.324-68 3,250,990 5/1966 Hubbs et al. 324-68 X 3,437,834 4/1969 Schwartz328-1l0 X 2,685,687 8/1954 Falk 32468 XR FOREIGN PATENTS 969,972 6/ 1950France.

OTHER REFERENCES Scray, Automatic Rise Time Measurement, IBM TechnicalDisclosure Bulletin, vol. 2, No. 6, April 1960, p. 47.

ALFRED E. SMITH, Primary Examiner U.S. Cl. X.R. 307235

